I’m implementing a uart daisy-chain communication scheme with a Cortex M4.
When a node receives a byte over one UART, an interrupt is generated (RXNE) and the byte is written out over another UART – since I use a send and receive buffer, this places the byte in the send buffer and enables the TXE interrupt which should be triggered subsequently.
This means for every byte received, two interrupts are triggered.
Now both UARTs can receive and transmit, and it is very much possible that both UARTs do receive a byte at the same time – now both will get a RXNE interrupt and trigger a TXE interrupt on the other UART.
But only one ISR can be processed at the same time – what happens with the other ones?
Is there an interrupt stack that can get full or interrupts simply called until all corresponding interrupt bits are cleared?
The thing is that my application tends to lock up under the situation described above (with multiple bytes being received). Not however when the UARTs are set to a lower speed (this seems counter intuitive) or when there is only one side connected.